With a recent demand for increases in the density and level of integration of semiconductor devices, there has been a demand for formation of finer patterns in a fabrication process for a semiconductor circuit. Typically, semiconductor devices whose density and level of integration are increased often have a multilayer wiring structure in which a plurality of wiring layers are formed on a substrate while being isolated from one another by associated insulating films. Wiring layers forming part of such a semiconductor device need to be finely patterned in an exposure process step of the fabrication process. When the top surface of a substrate on which a pattern mask is placed is uneven and has low flatness, this reduces the resolution of the exposure process step. As a result, a fine pattern cannot be formed. When the degree of wiring congestion significantly varies among regions of a certain wiring layer, this makes it difficult to completely planarize the top surface of a substrate even by CMP. To cope with this, a dry etching process must keep the states of chips on a wafer being etched always fixed. To do this, dummy patterns (alternatively, referred to as dummy metals) called dummy wirings must be placed in regions of a wiring having low degrees of wiring congestion, thereby allowing each chip to have the same area ratio (aperture ratio).
Accordingly, dummy patterns are additionally formed on regions of a substrate in which the interwiring distance is wide. The existence of such patterns produces additional capacitance for peripheral wirings. Consequently, a malfunction, noise generation and other causes all arising from fluctuations in the capacitance of a signal wiring pattern affect the circuit characteristics. For present high-performance semiconductor integrated circuits, it is an important challenge to reduce the coupling capacitance during the layout design phase. It can be said as one of very important challenges in terms of timing design to, even when additional capacitance is produced by additionally forming dummy patterns, reduce the additional capacitance as much as possible or equalize the additional capacitance.
Additional capacitance arising from the existence of such dummy patterns can be reduced by locating the dummy patterns away from an associated wiring pattern as much as possible. However, since dummy patterns are originally intended to be located in the gaps between adjacent pairs of wirings, the distance between each adjacent pair of wiring patterns is limited. In a case where dummy patterns are uniformly a fixed distance away from arbitrary wiring patterns, additional capacitance becomes uneven. The reason for this is that each additional capacitance depends on the size of an associated wiring pattern. To cope with the above-mentioned problem, the following method has been disclosed, as a known technique for additionally forming dummy patterns, in Patent Document 3: The distance between a signal wiring pattern and an associated dummy pattern is set according to the width of the signal wiring pattern, and when the distance therebetween is smaller than the set distance, this restrains the dummy pattern from being placed. This method can not only prevent the proportion of dummy metals on a predetermined area of each chip (aperture ratio) from being locally reduced but also avoid a deterioration in the performance of a signal associated with an existing wiring pattern due to the formation of dummy patterns. Furthermore, as disclosed in Patent Document 2, there is also a technique in which the locations of dummy patterns formed in different layers are prevented from coinciding with one another when viewed in plane, thereby reducing additional capacitance. In general, in cases where respective patterns formed in upper and lower layers coincide with each other when viewed in plane or in cases where patterns formed in the same layer are laterally adjacent to each other, a large capacitance is added to a signal wiring pattern. On the other hand, in cases where respective patterns in different upper and lower wiring layers are diagonally placed so as to be prevented from coinciding with each other when viewed in plane, capacitance is hardly produced between the patterns. A technique utilizing this physical phenomenon has been disclosed in Patent Document 2.
Meanwhile, it is one of solutions to equalization of additional capacitance to always maintain the same spatial relationship between a wiring pattern and an adjacent dummy pattern. The following technique has been disclosed, as a known technique for additionally forming dummy patterns, in Patent Document 1: Dummy patterns each form the shape of a cross, and the length of each of extending parts of this cross can be arbitrarily changed. According to this technique, additional capacitance added to the existing wiring pattern can be substantially equalized independently of the location of an existing wiring pattern formed in a wiring layer above or below these dummy patterns forming the shape of a cross. Furthermore, even when the existing wiring pattern is not disposed on a wiring grid, the intervals between dummy patterns and wiring patterns can be freely set at a predetermined value by arbitrarily changing the length of the extending part of the cross, thereby equalizing the intervals.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 6-61230 (page 3, FIG. 1)
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2002-231815 (page 5, FIG. 1)
Patent Document 3: Japanese Unexamined Patent Application Publication No. 2003-282569 (page 9, FIG. 1)